| Autor: |
Hoi-Jun Yoo, Seung-Jun Lee, Kee-Woo Park, Chang-Ho Chung, Kye-Hwan Oh, Sang-Ho Shin, Ki-Hong Park, Jeong-Dong Han, Seok-Tae Kim, Jin-Seung Son, Wi-Sik Min |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
Digest of Technical Papers., Symposium on VLSI Circuits.. |
| DOI: |
10.1109/vlsic.1995.520711 |
| Popis: |
A 32 bit-wide 256 M synchronous DRAM (SDRAM) has been developed. The major design effort has been focused on minimizing the operating current at high clock frequencies to suppress power-line bouncing. The key techniques are split-bank architecture, multiplexed global address-bus with local column address counter, column-decoded data-line, and global data-bus architecture with reduced voltage swing. Simulation shows the reduction in the operating current at 200 MHz is up to 35% compared with a conventional scheme. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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