112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels
Autor: | Yevgeny Perelman, Yosi Sanhedrai, Ro'ee Eitan, Yoel Krupnik, Itamar Levin, Udi Virobnik, Alon Meisler, Ariel Cohen, Yoni Landau, Yizhak Shifman, Ahmad Khairi, Noam Dolev |
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Rok vydání: | 2020 |
Předmět: |
Computer science
020208 electrical & electronic engineering SerDes Equalization (audio) Equalizer 02 engineering and technology Analog front-end Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Bit error rate Electronic engineering Nyquist–Shannon sampling theorem Digitally controlled oscillator Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Transceiver Error detection and correction |
Zdroj: | IEEE Journal of Solid-State Circuits. 55:1077-1085 |
ISSN: | 1558-173X 0018-9200 |
DOI: | 10.1109/jssc.2019.2959511 |
Popis: | A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel’s 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-tap feed-forward equalizer (FFE), and a 1-tap decision-feedback equalizer (DFE), as well as a clock and data recovery (CDR) loop utilizing a 7-GHz digitally controlled oscillator (DCO). Long-reach, −35 dB Nyquist channels are supported by a pre-forward error correction (FEC) bit error rate (BER) of 1e-6, thus making it compatible with existing and projected IEEE Ethernet specifications. |
Databáze: | OpenAIRE |
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