| Autor: |
Chris Madden, Yi Lu, Liji Gopalakrishnan, Kashinath Prabhu, Scott C. Best, Kambiz Kaviani, Ravi Kollipara, Pravin Kumar Venkatesan, Ganapathy E. Kumar, Sanath Bangalore, Lei Luo, K. Vyas, Hai Lan, Michael Bucher, Sam Chang |
| Rok vydání: |
2013 |
| Předmět: |
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| Zdroj: |
2013 IEEE 63rd Electronic Components and Technology Conference. |
| DOI: |
10.1109/ectc.2013.6575751 |
| Popis: |
A memory system that meets the bandwidth, power efficiency, and capacity needs of future computing systems is presented in this paper. A 6.4 Gbps single-ended DDR memory interface for the controller and the DRAM was designed in a 28-nm CMOS process for a main memory system with dual-rank DIMMs. The architecture features a novel clocking scheme, per-pin timing adjustment, dynamic point-to-point signaling topology, and near ground signaling. The system V-T budget simulations and the characterization results of the fabricated memory interface are presented. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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