High-Performance System-on-Chip-Based Accelerator System for Polynomial Matrix Multiplications
Autor: | Soydan Redif, Server Kasap |
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Rok vydání: | 2019 |
Předmět: |
0209 industrial biotechnology
Polynomial Computational complexity theory Computer science Applied Mathematics Context (language use) Systolic array 02 engineering and technology Polynomial matrix Computational science 020901 industrial engineering & automation Factorization Signal Processing Scalability Multiplication |
Zdroj: | Circuits, Systems, and Signal Processing. 38:5755-5785 |
ISSN: | 1531-5878 0278-081X |
DOI: | 10.1007/s00034-019-01150-w |
Popis: | Polynomial matrix computations, such as polynomial matrix multiplication (PMM) and eigenvalue factorization of parahermitian matrices, have played an important role in a growing number of applications, in recent times. However, the computational complexity and expense of such operations impose a profound limit on their applicability. In a recent paper, we introduced a systolic array-based parallel architecture for PMM, which was adequately efficient, but limited in its application. In this paper, we propose a second-generation hardware solution which boasts more versatility, efficiency and scalability compared to our previous design. This is achieved through the design of a highly versatile PMM accelerator which supports polynomial matrices of any size, as a component of the embedded system developed within the Xilinx Zynq-7000 AP SoC. Experimental results demonstrate the efficiency and effectiveness of our novel SoC-based PMM accelerator in the context of subband coding, where maximum speedups of $$85\times $$ and $$33\times $$ are accomplished, without compromising the accuracy, in comparison with two highly optimized and multi-threaded software-only implementations running on a dual-core ARM Cortex-A9 processor and a Intel Core i7-4510U CPU, respectively. |
Databáze: | OpenAIRE |
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