Fully integrated multilevel interconnect process for low cost sub-half-micron ASIC applications

Autor:	M. Seto, M. Murota, K. Miyamoto, R. Ogawa, Minakshisundaran Balasubramanian Anand, Masahiro Inohara, M. Norishima, H. Ohtani, Masakazu Kakumu, K. Inoue, C. Fukuhara, Hideki Shibata, Tadashi Matsuno
Rok vydání:	2002
Předmět:	Interconnection Materials science Application-specific integrated circuit Etching (microfabrication) Process integration Hardware_INTEGRATEDCIRCUITS Electronic engineering Process (computing) Minification Dielectric Line (electrical engineering)
Zdroj:	1995 Symposium on VLSI Technology. Digest of Technical Papers.
DOI:	10.1109/vlsit.1995.520853
Popis:	Back-end-of-the line (BEOL) interconnect process integration for sub-half-micron ASIC applications with both low-cost merit and appropriately high performance is presented. Borderless and stacked contact/via structures to reduce chip size and minimization of ILD thickness without performance degradation are achieved. Blind-CMP, selective tungsten CVD, and fluorine-TEOS ILD with low dielectric constant are selected with process simplification in mind.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::6f6d23a65b7dabf989b8241229e4e4e0 https://doi.org/10.1109/vlsit.1995.520853 Zobrazit plný text záznamu