Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices

Autor:	M. Ieong, J. Sudijono, J.H. Ku, D. Shum, M. Hierlemann, R. Amos, G. Chiulli, R. Lindsay, S.D. Kim, R. Loesing, L. Burns, A. Turansky, A. Madan, B. St Lawrence, R. Davis, R. Murphy, J. Li, J.J. Kim, H. Zhuang, S. Mishra, D. Schepis, A. Gutmann, J. Kempisty, T.N. Adam, J. Holt, H. Ng, S. Fang, Y.F. Chong, R. Stierstorfer, R. Krishnasamy, Z. Luo, N. Rovedo, L.W. Teo, H. Utomo, J.P. Han
Rok vydání:	2006
Předmět:	chemistry.chemical_compound Materials science chemistry CMOS business.industry Silicide Electrical engineering Optoelectronics chemistry.chemical_element Germanium Parasitic extraction business
Zdroj:	2006 International Electron Devices Meeting.
Popis:	We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at Ioff = 100nA/mum with VDD = 1V. Competitive nFET performance was maintained. Parasitics such as silicide and junction characteristics were not degraded
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::6f69c8ec8089702df2e409185a015c70 https://doi.org/10.1109/iedm.2006.346958 Zobrazit plný text záznamu