An energy efficient 32nm 20 MB L3 cache for Intel® Xeon® processor E5 family

Autor:	Songnian He, Ramesh Arvapalli, Min Huang, Moty Mehalel
Rok vydání:	2012
Předmět:	Set (abstract data type) Engineering Xeon CPU cache business.industry Embedded system Topology (electrical circuits) Parallel computing Modular design business Metal gate Electrical efficiency Efficient energy use
Zdroj:	CICC
DOI:	10.1109/cicc.2012.6330624
Popis:	A 20-way set associative 20MB energy efficient L3 this paper. The design uses 0.2119um2 cell and is manufactured in the 32nm second generation of high-K dielectric metal gate process with 9-copper layers. The power efficiency was achieved by employing advanced power saving schemes and effective Vccmin design techniques. The proposed L3 cache topology seamlessly supports a high density modular and energy efficient designs.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::6f491ac5553b714df01d65daca2ee7b1 https://doi.org/10.1109/cicc.2012.6330624 Zobrazit plný text záznamu