| Autor: |
S Kamatchi, Degala Veera Venkata Sairam, Dhage Navaneet Rao, Ganne Sai Charan |
| Rok vydání: |
2021 |
| Předmět: |
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| Zdroj: |
2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT). |
| DOI: |
10.1109/icaect49130.2021.9392582 |
| Popis: |
A new data type called Posit is designed as a direct drop-in replacement for IEEE Standard 754 floating-point numbers (floats). Because of having high accuracy, better closure, simpler circuitry and better range it may replace the Floating-Point Unit (FPU) in all the digital systems. This posit number system comprises of bit fields exponent & regime which have no fixed bit field size as opposed to floating point system which has fixed bit length. This nature of posit system gives rise to many implementation challenges. Since this is a neoteric development it lacks for hardware arithmetic developments. So this paper targets posit arithmetic Division algorithm development.The proposed Posit Division algorithm is implemented in Xilinx ISE Design Suite |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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