An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies
Autor: | Cristian Carmona, Bartomeu Alorda, S.A. Bota, G. Torrens |
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Rok vydání: | 2016 |
Předmět: |
Engineering
02 engineering and technology 01 natural sciences law.invention Reliability (semiconductor) law 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering Static random-access memory Electrical and Electronic Engineering Safety Risk Reliability and Quality 010302 applied physics business.industry 020208 electrical & electronic engineering Transistor Condensed Matter Physics Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials CMOS Metric (mathematics) business Word (computer architecture) Voltage drop Voltage |
Zdroj: | Microelectronics Reliability. 65:280-288 |
ISSN: | 0026-2714 |
DOI: | 10.1016/j.microrel.2016.07.154 |
Popis: | Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics require including test structures that cannot be used to investigate cell bit fails in functional SRAM arrays. This work proposes the Word Line Voltage Margin (WLVM), defined as the maximum allowed word-line voltage drop during write operations, as a metric for the experimental characterization of write stability of SRAM cells. Their experimental measurement can be attained with minimal design modifications, while achieving good correlation with existing writability metrics. To demonstrate its feasibility, the distribution of WLVM values has been measured in an SRAM prototype implemented in 65 nm CMOS technology. The dependence of the metric with the width of the transistors has been also analysed, demonstrating their utility in post-process write stability characterization. |
Databáze: | OpenAIRE |
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