Immersion resist process for 32-nm node logic devices

Autor: Akiko Yamada, Shoji Mimotogi, Kotaro Fujii, Hiroki Yonemitsu, Akiko Nomachi, Tatsuhiko Ema, Shinichi Ito, Satoshi Nagai, Hiroharu Fujise, Yuriko Seino, Fukushima Takashi, Toshiaki Komukai, Koutarou Sho, Yosuke Kitamura, Tsukasa Azuma
Rok vydání: 2008
Předmět:
Zdroj: Advances in Resist Materials and Processing Technology XXV.
ISSN: 0277-786X
DOI: 10.1117/12.771008
Popis: Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node advances. The target of reflectivity control over existent substrate thickness variation is 0.4%, which was estimated from our dose budget analysis. Then, single BARC process or stacked mask process (SMAP) was selected to each of the critical layers according to the substrate transparency. Another key issue in terms of material process was described in this paper, that is spin-on-carbon (SOC) pattern deformation during substrate etch process. New SOC material without any deformation during etch process was successfully developed for 32nm node stacked mask process (SMAP). 1.3NA immersion lithography and pattern transfer performance using single BARC
Databáze: OpenAIRE