Yield model for ASIC and processor chips
| Autor: | C.H. Stapper, R.J. Rosner, J.A. Patrick |
|---|---|
| Rok vydání: | 2002 |
| Předmět: |
Engineering
Hardware_MEMORYSTRUCTURES Yield (engineering) business.industry Semiconductor device modeling Hardware_PERFORMANCEANDRELIABILITY CMOS Application-specific integrated circuit Embedded system Logic gate Hardware_INTEGRATEDCIRCUITS Static random-access memory business Dram Electronic circuit |
| Zdroj: | DFT |
| DOI: | 10.1109/dftvs.1993.595739 |
| Popis: | Yield models based on chip area are inadequate for modeling the yield of CMOS ASIC and processor chips. A model based on the number of circuits was found to give more accurate results. Defect learning curves measured with DRAMs have been used successfully to project the yield of a wide variety of chips. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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