Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array

Autor:	Guilhem Larrieu, N. Clement, Youssouf Guerfi, Xiang-Lei Han
Rok vydání:	2015
Předmět:	Materials science Fabrication business.industry Transistor Nanowire Nanotechnology Hardware_PERFORMANCEANDRELIABILITY Nanowire array law.invention CMOS law Hardware_INTEGRATEDCIRCUITS Optoelectronics business Layer (electronics) Nanoscopic scale Scaling Hardware_LOGICDESIGN
Zdroj:	ESSDERC
DOI:	10.1109/essderc.2015.7324750
Popis:	A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations both in processing (layer engineering at nanoscale), in electrical properties (high electrostatic control, low defect level, multi-Vt platform) in the fabrication of CMOS inverters and in the perspective of ultimate scaling.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::6e22fd84f488b7e9b752c49ad61ad845 https://doi.org/10.1109/essderc.2015.7324750 Zobrazit plný text záznamu