A 6 $\mu$ W 95 dB SNDR Inverter Based $\Sigma\Delta$ Modulator With Subtractive Dithering and SAR Quantizer
| Autor: | Baozhen Chen, Huajun Zhang, Roberto S. Maurino, Khiem Quang Nguyen, Yi Zhang, Robert Adams, Zhichao Tan |
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| Rok vydání: | 2019 |
| Předmět: |
Physics
Transconductance Amplifier 020208 electrical & electronic engineering ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION 02 engineering and technology Delta-sigma modulation Topology 03 medical and health sciences 0302 clinical medicine CMOS Modulation Integrator 0202 electrical engineering electronic engineering information engineering Inverter Dither Electrical and Electronic Engineering 030217 neurology & neurosurgery |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 66:552-556 |
| ISSN: | 1558-3791 1549-7747 |
| DOI: | 10.1109/tcsii.2018.2869103 |
| Popis: | This brief presents a low-power $ {\Sigma \Delta }$ modulator using the subtractive dither technique. The proposed technique eliminates tones at the $ {\Sigma \Delta }$ modulator’s output by injecting a dither into the quantizer. The injected dither is cancelled at the first integrator’s output, which results in minimal impact on the operational transconductance amplifiers’ (OTAs) output swings and enables the use of energy-efficient inverter-based OTAs. Dither is also subtracted from the digital output and has no impact on the signal-to-quantization-noise ratio. The modulator features a successive approximation register quantizer and a modified DAC which eliminates signal-dependent kick-back to the input and reference buffers. Implemented in 180-nm CMOS, the proposed modulator achieves 95.1 dB signal-to-noise-and-distortion ratio from dc to 1 kHz, and consumes only 6 $ {\mu }\text{W}$ from a 1.2-V supply according to transient noise simulation, leading to a state-of-the-art Schreier figure-of-merit of 177.3 dB. Simulation verifies the effectiveness of subtractive dither. |
| Databáze: | OpenAIRE |
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