| Popis: |
The proper management of resources available in FPGA’s is one of the main issues that designers must consider when implementing a high bandwidth communications system. For this reason, we report the hardware-efficient implementation, for mapping stages and pulse shaping, of broadband multi-level QAM signals, in Field-Programmable Gate Array (FPGA) devices. The process for designing the system is based on the large capacity of analog-digital (ADC) converters that exist today, in this case the ADC has a sampling rate of 5 GSPS, which allows the transmission of signals with bandwidths of about 2.5 GHz. The model implements in the same polyphase FIR structure multiplier-less the mapping schemes Q-PSK, 16-QAM, 64-QAM y 256-QAM together with the RRC filter. As a result, this implementation shows that the proposed architecture eliminates the use of dedicated multipliers which would be around 3150 if conventional methods were used. The Error Vector Module is used as a figure of merit in the selection of the RRC filter and the digital quantization levels. We achieved the target frequency for hardware operation at 312.5 MHz con un factor de interpolation de 16 and an EVM < 2%. Also, Hardware Description Language (HDL) models are validates in test benches with reference to the finite precision models of Simulink. |
