A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
| Autor: | Yongping Han, Yongrong Zuo, Chih-Wei Yao, Ashutosh Verma, Pei-Yuan Chiang, Wanghua Wu, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho, Kunal Godbole, Ronghua Ni |
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| Rok vydání: | 2019 |
| Předmět: |
Physics
Frequency band 020208 electrical & electronic engineering Linearity 02 engineering and technology Phase-locked loop QAM Sampling (signal processing) Duty cycle Phase noise 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Jitter |
| Zdroj: | IEEE Journal of Solid-State Circuits. 54:1254-1265 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured fractional spur is less than −64 dBc across the 5.5–7.3-GHz output frequency band. The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellular 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting $2 \times 2$ multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm2. |
| Databáze: | OpenAIRE |
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