Design and implementation of area efficient EAIC modulo adder
| Autor: | S. Saravanan, Anjali S. Pillai, Thiruvenkadam Krishnan, Parthibaraj Anguraj |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Very-large-scale integration Adder Digital signal processor business.industry Computer science Carry (arithmetic) Modulo 02 engineering and technology General Medicine 021001 nanoscience & nanotechnology Residue number system 01 natural sciences Application-specific integrated circuit 0103 physical sciences Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic 0210 nano-technology business Digital signal processing |
| Zdroj: | Materials Today: Proceedings. 33:3751-3756 |
| ISSN: | 2214-7853 |
| DOI: | 10.1016/j.matpr.2020.06.172 |
| Popis: | The addition of binary numbers is the fundamental and most often used arithmetic operation on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Binary adders are the crucial building blocks in very large-scale integrated (VLSI) circuits. Modular adders are fundamental arithmetic components typically employed in residue number system (RNS)-based digital signal processing (DSP) systems. In this paper, modified End-Around Inverted Carry (EAIC) area-efficient modulo adder is designed using various parallel prefix adders. In the proposed design, parallel prefix operation and carry correction techniques are adopted to eliminate the re-computation of carries. Compared with the same type of modulo adder structure, the proposed designs offer reduced area and delay reduced compared to the existing design. |
| Databáze: | OpenAIRE |
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