Reliability Challenges in 2.5D and 3D IC Integration
| Autor: | Paul Ton, Li Li, Pierre Chia, Mohan Nagar |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Engineering
Moore's law Packaging engineering business.industry media_common.quotation_subject 0211 other engineering and technologies Three-dimensional integrated circuit 02 engineering and technology 020202 computer hardware & architecture Reliability engineering Form factor (design) System in package Reliability (semiconductor) Embedded system 0202 electrical engineering electronic engineering information engineering System integration Integrated circuit packaging business 021106 design practice & management media_common |
| Zdroj: | 2017 IEEE 67th Electronic Components and Technology Conference (ECTC). |
| Popis: | Today, applications like data center/cloud, mobility and Internet of Things (IoT) are key market drivers for semiconductor industry. To meet the requirements of next generation Information and Communication Technology (ICT) systems, the packaging technology has to evolve along with the Integrated Circuit (IC) technology scaling. At the same time, design and development of packages have to meet the cost, performance, form factor and reliability goals. In this paper, we will examine new advances in packaging technology to maintain the IC scaling edge, as well as the role of new emerging 2.5-dimensional (2.5D) and 3-dimensional (3D) IC packaging platforms for addressing the gap seen between the slowdown of Moore's Law scaling and the ever-increasing system integration requirements. We will then review the new elements introduced by 2.5D and 3D IC integration and the potential risks to reliability of the final products. A detailed review on technology and component level qualification will be presented. It will then be followed by three case studies on board level reliability validation. One case is about evaluating a Dual In-line Memory Module (DIMM) with 3DS DDR3 for server applications. The second case is on a 3D IC package with 5 dice stacked and interconnected with Through-Silicon-Vias (TSV). And the third package is a 3D System-in-Package with multiple 3D die-stacks packaged with an organic interposer. The results from reliability testing are used to understand the driving forces and failure mechanism acceleration and to define the application space of the 3D IC packages for networking applications. |
| Databáze: | OpenAIRE |
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