Automatic Software-Based Self Test Generation for Embedded Processors
| Autor: | Ján Hudec |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Reduced instruction set computing Computer science business.industry Code coverage 02 engineering and technology 01 natural sciences 020202 computer hardware & architecture Test (assessment) Instruction set Software Control and Systems Engineering Embedded system 0103 physical sciences Metric (mathematics) VHDL 0202 electrical engineering electronic engineering information engineering business computer computer.programming_language |
| Zdroj: | IFAC-PapersOnLine. 51:125-130 |
| ISSN: | 2405-8963 |
| Popis: | The paper deals with automatic software-based test generation for processors. Processors are basic blocks of current complex systems on chip and embedded systems. Processors testing can be extended by functional tests or using various application programs. Such types of tests are serving as additional tests to structural testing or as tests used in verification. Functional tests (programs) are generated over an instruction set architecture and processor model description. A metric for quality evaluation of the software-based tests is obviously provided by code coverage of a processor model. A new functional test generation method is based on VHDL model of processors and genetic algorithms with using various evolutionary strategies. The contribution to the SBST methods based on GAs using the latest defined ES was identified. Functionality and effectiveness of the developed methods were evaluated in the implemented system AGenMIX over two types of RISC processor. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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