A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks

Autor: Cesar Henzelin, David Ruffieux, Daniel Severac, Steve Gyger, Budhaditya Banerjee, Nicola Scolari, Francois Kaess, Erwan Le Roux, Matteo Contaldo, Marc Morgan, Jean-Félix Perotto, V. Peiris, Thanh-Chau Le, Pascal Heim, Alexandre Vouilloz, Patrick Volet, Claude Arm, Daniel Sigg, Cedric Monneron, Frederic Giroud, Nicolas Raemy
Rok vydání: 2010
Předmět:
Zdroj: ISSCC
DOI: 10.1109/isscc.2010.5433848
Popis: Wireless Sensor Networks (WSN) and in particular Wireless Body Area Networks (WBAN) require long autonomy and miniature integrated solutions. While the autonomy in WSN is mostly limited by the energy consumption of the radio [1], WBAN rely on sensors whose power consumption may not be neglected. In such cases, the use of an external DSP for compression of the sensor information would enable to optimize the signal processing power efficiency, but would not help for the miniaturization and the overall low power consumption, because such parts are not optimized for low power as high-speed digital signals need to be driven off- and on-chip. A major challenge is thus to embed a low-power DSP core with the radio on an SoC for enabling multi-year autonomy while running on supplies as low as 1V for alkaline cells. Previous publications confirm the need for 1V CMOS radio SoCs, such as [2] and [3] which combine a low-power short-range radio with an 8-bit micro-controller on-chip but lack digital signal-processing capability. Solutions such as [4] have been proposed recently and embed a 16b MCU with a radio, but cannot be operated below 1.8V. This paper describes a fully integrated SoC that embeds, on a single die, a radio with a 32b low-power DSP core and a comprehensive set of analog/digital peripherals, while being compliant with as low as 1V supply. The main functions of the SoC, which are highlighted in the block diagram of Fig. 25.8.1, are described in the next sections.
Databáze: OpenAIRE