A sub-10-ns 16×16 multiplier using 0.6-μm CMOS technology

Autor: Shigeyoshi Watanabe, Naoko Takenouchi, Hiroshi Takato, Kazunori Ohuchi, Kazushi Tsuda, A. Hojo, Kenji Tsuchiya, Kenji Numata, Akihiro Nitayama, Yukihito Oowaki, M. Chiba, T. Kobayashi
Rok vydání: 1987
Předmět:
Zdroj: IEEE Journal of Solid-State Circuits. 22:762-767
ISSN: 0018-9200
Popis: A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.
Databáze: OpenAIRE