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High-end, high-performance computers use high-speed serial interfaces to pass data and control signals between the electronic components in the systems. These interfaces include proprietary interfaces unique to a class of systems and some interfaces, such as PCIe & SAS, which have publicly available standards and specifications that enable communication between electronic components from different manufactures. The IBIS-AMI model has been developed to facilitate circuit simulation of high-speed serial interfaces and is particularly useful in simulating communication between transmitters and receivers procured from different manufactures. The simulations are performed to ensure that the interface specifications are met, including the eye characteristics, and that the bit error rate (BER) is less than a specified maximum. There are many variables and long bit strings needed to predict a BER of sufficiently low amplitude. Therefore, an efficient and accurate estimation of BER requires significantly long simulations times. In this paper, we use the example of a 6 gigabit per second (Gb/s) SAS interface to illustrate our proposed simulation method of combining an empirical and analytical approach to estimate the effects of inter-symbol interference (ISI) and channel jitter using an IBIS-AMI models. |
