Mobility enhancement of SSOI devices fabricated with sacrificial thin relaxed SiGe

Autor:	J.S. Maa, D.J. Tweet, Jong-Jan Lee, S.T. Hsu
Rok vydání:	2005
Předmět:	Electron mobility Ion implantation Materials science business.industry Wafer bonding MOSFET Electronic engineering Optoelectronics Silicon on insulator Wafer business NMOS logic PMOS logic
Zdroj:	2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
DOI:	10.1109/soi.2004.1391590
Popis:	NMOS and PMOS devices have been successfully fabricated on SSOI wafers with a 20 nm strained Si layer. The electron and hole mobility enhancements are 115% and 45%, respectively. The SSOI wafer was fabricated by direct wafer bonding with the strained Si on thin SiGe (300 nm) virtual substrate transferred to the oxidized handle wafer by splitting. Strained SiGe depositing H/sub 2//sup +/ implantation, and SiGe lattice relaxation annealing are sequentially performed for the thin SiGe virtual substrate fabrication.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::6aff161c67521ddc087a1b9dbf2bd9fb https://doi.org/10.1109/soi.2004.1391590 Zobrazit plný text záznamu