Design of Low Power, Low Jitter PLL for WiMAX Application in 0.18µm CMOS Process
| Autor: | R. V. Kshirsagar, Aniruddha C. Kailuke, Pankaj Agrawal |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Computer science
Linearity 020206 networking & telecommunications Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Feedback loop Frequency divider Phase-locked loop Voltage-controlled oscillator CMOS Phase noise Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Charge pump General Earth and Planetary Sciences 020201 artificial intelligence & image processing Phase frequency detector General Environmental Science Jitter |
| Zdroj: | Procedia Computer Science. 152:390-397 |
| ISSN: | 1877-0509 |
| DOI: | 10.1016/j.procs.2019.05.001 |
| Popis: | A low power, low jitter high performance Phase Locked Loop (PLL) based on closed loop Phase Frequency Detector (PFD) and novel Gain-Boosting Charge Pump (GB-CP) technique are shown in this study. The proposed work for WiMAX application is simulated using Tanner 13 tool using a 0.18µm CMOS technology. The current starved VCO is used to improve the linearity and phase noise of PLL. In feedback loop master-slave divided-by-2 frequency divider circuit is used to achieve a maximum speed with minimum power dissipation. The simulation result shows that total power consumption is 3mW at 1.8V power supply at maximum frequency of 2.4 GHz and RMS jitter is 3ps. The locking time of proposed PLL is 300ns, designed PLL is much suitable for WiMAX application |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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