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This chapter gives a short introduction to reconfigurable devices (Field-Programmable Gate Arrays—FPGA and hardware programmable Systems-on-Chip—SoC), design languages, methods, and tools that will be used in the book. The core reconfigurable elements and the most common embedded blocks are briefly characterized. A generic design flow is discussed and some examples are given that are ready to be tested in FPGA/SoC-based prototyping boards. All the subsequent chapters of the book will follow the suggested design methodology that includes: (1) proposing and evaluating basic architectures that are well suited for hardware accelerators; (2) modeling the chosen architectures in software (in Java language); (3) extracting the core components of future accelerators and generating (in software) fragments for synthesizable hardware description language specifications; (4) mapping the software models to hardware designs; (5) synthesis, implementation, and verification of the accelerators in hardware. The first chapter gives minimal necessary details and the background needed for the next chapters. All circuit specifications will be provided in VHDL. We will use Xilinx Vivado 2018.3 as the main design environment but will try to keep the proposed circuit specifications as platform independent as possible. An overview of the problems addressed in the book is also done and an introduction to different kinds of network-based processing is provided. |
