A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory
| Autor: | HyunWook Park, Doohyun Kim, Jae Doeg Yu, Hyun-Jun Yoon, Jonghoon Park, Kye-Hyun Kyung, Hyung-Gon Kim, Jinbae Bang, Chulbum Kim, Jeong-Don Ihm, Yong-Ha Park, Seung-Bum Kim, Woopyo Jeong, Hwajun Jang, Ji-Young Lee, Il Han Park, Nahyun Kim, Pansuk Kwak, Yang-Lo Ahn, Ki-Tae Park, Jong-Hoon Lee, Sanggi Hong, Hyun-Jin Kim, Park Jiyoon, Dae Seok Byeon, Jin-Yub Lee, Young-don Choi, Moosung Kim, Nayoung Choi, Seung-Hwan Song |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
business.industry Computer science Nand flash memory Logic gate 0103 physical sciences 0202 electrical engineering electronic engineering information engineering 02 engineering and technology Electrical and Electronic Engineering business 01 natural sciences Computer hardware 020202 computer hardware & architecture |
| Zdroj: | IEEE Journal of Solid-State Circuits. 53:124-133 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | A 64-word-line-stacked 512-Gb 3-b/cell 3-D NAND flash memory is presented. After briefly examining the challenges that occur to a stack, several technologies are suggested to resolve the issues. For performance enhancement, a novel program method hiding two-page data loading time is presented. This paper also discusses an electrical annealing improving reliability characteristic by removing holes in shallow traps. In addition, a valley tracking read for reducing timing overhead at a read retry is introduced by fast finding optimal read levels. Finally, a high-speed self-test mode for IO operation is presented. The chip, designed with the fourth generation of V-NAND technology, achieved an areal density of 3.98 Gb/mm2 and operated up to 1 Gb/s at 1.2 V. |
| Databáze: | OpenAIRE |
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