High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols
| Autor: | Shih-Chieh Chang, Hsuan-Ming Chou, Tien-Fu Chen, Keng-Hao Yang, Jean Tsao, Wen-Ben Jone, Yi-Chiao Chen |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Very-large-scale integration
Single chip Interconnection Engineering Out-of-order execution Deadlock free business.industry 02 engineering and technology Deadlock 020202 computer hardware & architecture Hardware and Architecture Embedded system 0202 electrical engineering electronic engineering information engineering System on a chip Electrical and Electronic Engineering business Database transaction Software |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:1169-1173 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2015.2430877 |
| Popis: | In a modern system-on-chip design, hundreds of cores and intellectual properties can be integrated into a single chip. To be suitable for high-performance interconnects, designers increasingly adopt advanced interconnect protocols that support novel mechanisms of parallel accessing, including outstanding transactions and out-of-order completion of transactions. To implement those novel mechanisms, a master tags an ID to each transaction to decide in-order or out-of-order properties. However, these advanced protocols may lead to transaction deadlocks that do not occur in traditional protocols. To prevent the deadlock problem, current solutions stall suspicious transactions and in certain cases, many such stalls can incur serious performance penalty. In this brief, we propose a novel ID assignment mechanism that guarantees the issued transactions to be deadlock-free and results in significant reduction in the number of transaction stalls issued by masters. Our experimental results show encouraging performance improvements compared with previous works with little hardware and power overheads. |
| Databáze: | OpenAIRE |
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