A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme
| Autor: | Tsuneo Takeuchi, T. Kunio, Yoichi Miyasaka, T. Otsuki, Takashi Hase, Yukihiko Maejima, K. Amantuma, M. Fukuma, N. Tanabe, Tohru Kimura, M. Takada, S. Kobayashi, Yoshihiro Hayashi, N. Shohata, T. Masuki, S. Saito, Hiroki Koike |
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| Rok vydání: | 1996 |
| Předmět: |
Computer science
Sense amplifier Registered memory Semiconductor memory Capacitance Ferroelectricity Ferroelectric capacitor law.invention Non-volatile memory Capacitor law Hardware_INTEGRATEDCIRCUITS Electronic engineering Bubble memory Racetrack memory Non-volatile random-access memory Electrical and Electronic Engineering Memory refresh Voltage reference Computer memory Dram |
| Zdroj: | IEEE Journal of Solid-State Circuits. 31:1625-1634 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/jssc.1996.542307 |
| Popis: | This paper proposes three circuit technologies for achieving mega-bit-class nonvolatile ferroelectric RAMs (NVFRAMs). The proposed nondriven cell plate line write/read scheme (NDP scheme) accomplishes fast write/read operation equivalent to that of DRAMs. Problems and countermeasures in introducing this scheme into NVFRAMs are also discussed. A proposed optimized C/sub B//C/sub S/ cell array design method provides a relationship between bit line capacitance C/sub B/ and memory cell capacitance C/sub S/, which must be satisfied for read operations. Also reported is a reference voltage generator circuit that uses a dummy memory cell. This circuit can generate an accurate reference voltage despite the variety of capacitors with differing characteristics that are contained in the NVFRAM. A 1-Mb NVFRAM prototype featuring the above technologies has been fabricated, using a 1.0-/spl mu/m CMOS process. This chip has an access time of 60 ns and a die size of 15.7/spl times/5.79 mm/sup 2/. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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