| Popis: |
With the signal speeds doubling for every generation, PCB design is becoming more and more challenging. The high-speed signal is getting more sensitive to the board layout impairments due to the dense placement of components. Therefore, a comprehensive scan including geometry, crosstalk, and noise coupling is necessary to ensure a quality eye at the receiver end for the concerned high-speed nets at 56Gb/s and beyond. In this paper, we offer a complete and automated full-board SI scan methodology. With such a methodology, subtle board layout defects are quickly pinpointed, including ground coverage, via stub length, trace necking, power via to signal via/trace spacing, and ground via to signal via distance, etc. Moreover, high-speed return loss and crosstalk scan in connector and ASIC pin fields are also implemented in an automated way with the help of the fast EM solver technology. As a result, the goal to have a confident PCB sign-off for the high-speed signals is achieved. |
