High Accuracy Thermal Compression Bonding Technology for Large-Sized Substrate
| Autor: | Mikio Kawakami, Yoshihito Mizutani, Hikaru Tomita, Hashimoto Yasunori, Imai Koichi, Masafumi Senda, Katsumi Terada, Toshiyuki Jinda, Noboru Asahi |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Engineering Wire bonding business.industry 05 social sciences Mechanical engineering Thermocompression bonding Substrate (printing) 01 natural sciences 0103 physical sciences Electronic engineering 0501 psychology and cognitive sciences Wafer Integrated circuit packaging Tape-automated bonding business Wafer-level packaging Flip chip 050104 developmental & child psychology |
| Zdroj: | 2017 IEEE 67th Electronic Components and Technology Conference (ECTC). |
| Popis: | For improvement of the productivity and the cost reduction, FOWLP (fan-out wafer level package) or FOPLP (fan-out panel level package) process using large-sized substrate has been actively developed in recent years. Above all, we will report about the novel TCB (thermal compression bonding) equipment which is even applicable to a 3D-IC stacking process and a fine pitch FOWLP or FOPLP of RDL-first process using large-sized substrate. We made the prototype which was applicable to CoW of 12 inch wafer and evaluated it. The prototype includes a high rigid fixed stage which is designed to the same size as the bonding head, and a substrate handling mechanism which lifts a substrate from the stage and transfers it to other prescribed position every one bonding cycle. By using this equipment, it is possible to thermally press a chip on even large-sized substrate without causing deterioration in bonding accuracy resulting from stage distortion. Also, it does not need to manage UTOS (Underfill time on stage), when the equipment is used for "2 step bonding process" which can improve the throughput of TCB. In this presentation, we will report about the investigation result of the heat influence on adjacent chip and about the temperature difference in the 3D-IC stacking process by using the prototype. In addition, we will present a novel multi-layer collecting bonding process which is applicable to a large-sized substrate effectively, and report about the result of the evaluation of solder connection of the TSV TEG chip. |
| Databáze: | OpenAIRE |
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