| Autor: |
Janusz Rajski, Yu Huang, Jihye Kim, Dongkwan Han, Kun Young Chung, Mark Kassab, Jay Jahangiri, Wu-Tung Cheng |
| Rok vydání: |
2014 |
| Předmět: |
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| Zdroj: |
NATW |
| Popis: |
This paper proposes an innovative test compression technology for system-on-chip (SoC) designs to share scan input channels across multiple cores which use EDT [1] compression. A new DFT compression architecture is proposed to separate control and data channels such that the control channels can be individually accessible, whereas data channels can be shared among a group of cores. The paper illustrates the benefits of the proposed technology in both the enhancement of compression ratios and the flexibility of test compression planning in a core-based SoC design flow. Experimental results with a few large industrial SoCs demonstrate that using the proposed technology the compression can be improved up to 1.87X. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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