| Popis: |
There is growing demand for wafer level packaging, which enables thinner, lighter, and more cost effective packaging solutions. However, these demands come with a penalty; reduced package footprint limits the number of I/Os that can be realized in the smaller formfactor. In order to compensate this drawback, wafer level packaging fan-out has been drawing great attention, since fanning out of RDL beyond the die domain not only allows a higher number of I/Os without increasing the die size, but also allows to mount other passives or chips within the package. Compared to conventional packages, a significantly thinner formfactor is thereby achieved. Without a substrate, the wafer level packaging fan-out interacts directly with the Printed Circuit Board (PCB). Like conventional flip chip packages, which are designed and manufactured to mitigate chip package interaction risks, wafer level packaging fan-out needs to be designed and manufactured to mitigate chip board interaction risks. To address this challenge, a test vehicle was designed and manufactured based on silicon on insulator technology. Drop and temperature cycling test on board were performed on the assembled test vehicle. To understand the failure mechanisms, failure mode analysis and Weibull analysis were performed. |
