| Popis: |
Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. We present a scalable current-based dynamic method to estimate both IR and Ldi/dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay caused by variations in power-supply voltage. This increase in delay can cause significant overkill during transition and delay testing. It is critical to account for this increase in delay during the ATPG process. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. To overcome this issue, our technique uses simulations of individual extracted paths and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for the C6288 ISCAS'85 benchmark circuit are presented. Our technique can also be applied to sequential circuits and simulation results demonstrating this are also presented. |
