High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter
Autor: | Neeta Pandey, Asok Bhattacharyya, Ranjana Sridhar, Veepsa Bhatia |
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Rok vydání: | 2015 |
Předmět: |
Engineering
Differential nonlinearity General Computer Science Comparator business.industry 020208 electrical & electronic engineering 020206 networking & telecommunications 02 engineering and technology Propagation delay Flash ADC Process corners Comparator applications Integral nonlinearity Control theory Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Gain stage business |
Zdroj: | Journal of The Institution of Engineers (India): Series B. 97:147-154 |
ISSN: | 2250-2114 2250-2106 |
DOI: | 10.1007/s40031-015-0189-1 |
Popis: | This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage. The usefulness of the proposed comparator is demonstrated by implementing a 3-bit current mode flash analog-to-digital converter (ADC). Simulation program with integrated circuit emphasis (SPICE) simulations have been carried out to verify theoretical proposition and performance parameters of both comparator and ADC are obtained using TSMC 0.18 µm CMOS technology parameters. The current comparator shows a resolution of ±5 nA and a delay of 0.86 ns for current difference of ±1 µA. The impact of process variation on proposed comparator propagation delay has been studied through Monte Carlo simulation and it is found that percentage change in propagation delay in best case is 1.3 % only and in worst case is 9 % only. The ADC exhibits an offset, gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.102 µA, 0.99, −0.34 LSB and 0.0267 LSB, respectively. The impact of process variation on ADC has also been studied at different process corners. |
Databáze: | OpenAIRE |
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