Novel fine-grain back-bias assist techniques for 3D-monolithic 14 nm FDSOI top-tier SRAMs
| Autor: | Francois Andrieu, Joris Lacord, R. Berthelon, Laurent Brunet, A. Makosiej, Olivier Weber, C. Fenouillet-Beranger, X. Garros, G. Cibrario, D. Lattard, J.-P. Colinge, J. Cluzel, Lorenzo Ciampolini, D. Bosch, Perrine Batude, F. Balestra, Bastien Giraud |
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| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES Computer science Transistor Spice Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 021001 nanoscience & nanotechnology Condensed Matter Physics 01 natural sciences Capacitance Electronic Optical and Magnetic Materials law.invention Reduction (complexity) Planar law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS Materials Chemistry Electronic engineering Static random-access memory Back bias Electrical and Electronic Engineering 0210 nano-technology Access time |
| Zdroj: | Solid-State Electronics. 168:107720 |
| ISSN: | 0038-1101 |
| Popis: | For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm2 SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD = 0.8 V and a reduction of minimum operating voltage Vmin by 60 mV (up to 92 mV with speed penalty) at 6σ w.r.t. planar SRAMs. |
| Databáze: | OpenAIRE |
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