Design of a low power, high speed double tail comparator
| Autor: | J. P. Anita, G. Jaswanth Das, T. Abhiram, S. Aakash, A. Anisha |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Engineering
Comparator business.industry 020208 electrical & electronic engineering Transistor Electrical engineering Analog-to-digital converter Clock gating 02 engineering and technology 020202 computer hardware & architecture law.invention Power (physics) Comparator applications CMOS law 0202 electrical engineering electronic engineering information engineering Electronic engineering business Electronic circuit |
| Zdroj: | 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT). |
| DOI: | 10.1109/iccpct.2017.8074370 |
| Popis: | In the fast moving digital world, it becomes imperative to constantly come up with innovation in digitization. The analog to digital converter is the second most widely used device in the world of electronic circuits. ADCs are composed of dynamic comparators. To overcome the challenges faced due to the digital change, improved versions of the conventional comparator design for high-speed functioning and low power consumption has been proposed. Area is another main factor when keeping in mind the design of these dynamic comparators. 180 nm CMOS technology and a constant supply voltage of 0.8V have been used. A conventional double tail comparator has been designed by adding transistors without hindering the functionality. This provides faster, more efficient modification of the comparator design. A new design for a dynamic regenerative double-tail comparator has been proposed which uses clock-gating techniques. This further reduces the power consumption and provides higher speed by reducing the delay time of the circuit. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|