Advanced layout parameter extraction and detailed timing simulation of GaAs gate arrays in MagiCAD
| Autor: | Barry K. Gilbert, David O. Rowlands, Kevin J. Buchs, Jeffrey A. Prentice |
|---|---|
| Rok vydání: | 1990 |
| Předmět: | |
| Zdroj: | SPIE Proceedings. |
| ISSN: | 0277-786X |
| DOI: | 10.1117/12.21012 |
| Popis: | This paper discusses the features and function of three specific computer aided design tools contained in the Mayo Graphical Integrated Computer Aided Design (MagiCAD) system a complete electronic CAD software package optimized for the design and layout of semicustom (i. e. gate array) Gallium Arsenide (GaAs) integrated circuits. The first design tool the Layout Extractor processes data from placed and routed gate arrays. The Extractor verifies that the layout represents the original logic design and calculates the parasitic capacitance of the individual wiring segments in the logic nets after they have been routed. The capacitance information as calculated by the Layout Extractor is significant in GaAs work since the delay in signals traveling through the routing is often much greater than the delay of the signals traveling through the gates themselves. Once the capacitance data has been processed by the Layout Extractor it becomes available to the second CAD tool discussed here the MagiCAD timing simulation program Sting. Sting a digital event-driven simulator depends on user generation of C language-like behavioral models for all root nodes to be simulated. Through the use of delays calculated by the Extractor from the actual routing and input pin capacitances Sting assures that the entire chip design will operate correctly at the intended clock rate. The third design tool is a set of programs allowing simulation of the electromagnetic behavior of integrated circuit packages circuit© (1990) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|