Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGA
| Autor: | Venkat Reddy Ginjala, Maruthi Gillela, Vaclav Prenosil |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Password
Generator (computer programming) Computer science business.industry 020208 electrical & electronic engineering Hash function 020206 networking & telecommunications 02 engineering and technology Parallel computing MD5 Software Brute-force attack 0202 electrical engineering electronic engineering information engineering Hardware design languages Field-programmable gate array business |
| Zdroj: | VLSI Design |
| Popis: | FPGA implementation of MD5 hash algorithm is faster than its software counterpart, but a pre-image brute-force attack on MD5 hash still needs 2^(128) iterations theoretically. This work attempts to improve the speed of the brute-force attack on the MD5 algorithm using hardware implementation. A full 64-stage pipelining is done for MD5 hash generation and three architectures are presented for guess password generation. A 32/34/26-instance parallelization of MD5 hash generator and password generator pair is done to search for a password that was hashed using the MD5 algorithm. Total performance of about 6G trials/second has been achieved using a single Virtex-7 FPGA device. |
| Databáze: | OpenAIRE |
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