Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories
| Autor: | Chia-Yin Liu, Masanori Hariyama, Yi-Jung Chen |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Computer science business.industry 020207 software engineering Memory bandwidth Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Power (physics) Thermal aware 020204 information systems Embedded system Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering business Dram |
| Zdroj: | SAC |
| DOI: | 10.1145/3341105.3373858 |
| Popis: | Integrating Multi-Processor System-on-Chips (MPSoCs) and memories vertically by Through-Silicon Vias (TSVs) provides abundant memory bandwidth, but the increase of power density also makes the system frequently work under thermal emergent states. Although several thermal-aware TSV placement methods have been proposed to ease the thermal issue from the architectural design points of view, the overlooking of designing the type of stacked memories and memory interface in synergy may lead to thermal inefficient designs. The stacked memories may be SRAMs, DRAMs, or even NVMs, and they are divergent in power, performance, and thermal behavior, which in turn would greatly affect the memory interface design, i.e. TSV placements. In this paper, we propose the first thermal-aware memory system synthesis method for MPSoCs with 3D-stacked hybrid memories. The proposed method synergistically synthesizes the type of stacked memories and the memory interface aiming at optimizing performance while the thermal constraint is met. The results show that, among all the tested cases, the proposed method successfully keep peak temperature under 85°C with at most 29% of performance degradation. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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