| Autor: |
Jürg Treichler, Qiuting Huang, Thomas Burger |
| Rok vydání: |
2006 |
| Předmět: |
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| Zdroj: |
2006 Proceedings of the 32nd European Solid-State Circuits Conference. |
| ISSN: |
1930-8833 |
| Popis: |
This paper describes the implementation of a 10-bit ENOB 50-MS/s CMOS pipeline analogue-to-digital converter (ADC) in a 130-nm process with a supply voltage of 1.2 volts and on-chip voltage buffers. The pipeline stages are scaled in current and area consumption to five different sizes, and OTAs with double regulation provide high gain in the first four stages. A differential difference comparator architecture reduces the amount of needed MiM-capacitors. The converter reaches a dynamic range of 11 bits, and the total power consumption of the core is 122 mW. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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