A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
| Autor: | Yong Jyun Hu, Wei Hwang, Paul Sen Kan, Ming-Hsien Tu, Ching-Te Chuang, Chen Chien Hen, Li Wei Chu, Yang Hao I, Shyh-Jye Jou, Nan Chun Lien |
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| Rok vydání: | 2014 |
| Předmět: | |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers. 61:3416-3425 |
| ISSN: | 1558-0806 1549-8328 |
| DOI: | 10.1109/tcsi.2014.2336531 |
| Popis: | This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs boosted word-line (WL) for improving both read performance and write-ability. A ripple bit-line (RiBL) structure provides 30%-44% read access performance improvement and 2 ×-3.5 × variation immunity at 0.7 V compared with the conventional hierarchical bit-line (HiBL) schemes. An adaptive data-aware write-assist (ADAWA) with VCS tracking is employed to further enhance the write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An adaptive voltage detector (AVD) with binary boosting control is used to mitigating gate electric over-stress. The design is implemented in UMC 40 nm low-power (40LP) CMOS technology. The 512 kb test chip operates from 1.5 V to 0.65 V, with maximum operation frequency of 800 MHz@1.1 V and 200 MHz@0.65 V. The measured power consumption is 0.5 mW/MHz (active) and 4.4 mW (standby) at 1.1 V, and 0.107 mW/MHz (active) and 0.367 mW (standby) at 0.65 V. |
| Databáze: | OpenAIRE |
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