1/f Noise in CMOS transistors for analog applications from subthreshold to saturation
| Autor: | Yael Nemirovsky, Ilan Bloom, C.G. Jakobson |
|---|---|
| Rok vydání: | 1998 |
| Předmět: |
Noise temperature
Materials science business.industry Subthreshold conduction Noise spectral density Transconductance Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Condensed Matter::Mesoscopic Systems and Quantum Hall Effect Condensed Matter Physics Noise figure Electronic Optical and Magnetic Materials Burst noise Noise generator Hardware_INTEGRATEDCIRCUITS Materials Chemistry Optoelectronics Flicker noise Electrical and Electronic Engineering business Hardware_LOGICDESIGN |
| Zdroj: | Solid-State Electronics. 42:1807-1817 |
| ISSN: | 0038-1101 |
| Popis: | Detailed noise measurements of the 1/ f noise in p - and n -mos transistors for analog applications are reported under various bias conditions ranging from subthreshold to saturation. The CMOS transistors under study have a relatively large area, exhibit long channel behavior and are fabricated in a commercial “low noise process”, as prescribed for analog applications. A clear methodology and useful models for the power spectral densities of the gate voltage and drain current are presented and are based on recent studies in sub-micron transistors that have established the physical origin of 1/ f noise in MOS transistors. In saturation, it is found that it is advisable to limit the bias voltages to values that are experimentally determined from the transconductance characteristics and correspond to a nearly constant channel mobility. The experimentally observed reduction in channel mobility indicates the existence of strong fields that induce additional oxide charging and hence an increase in the effective density of oxide traps and the noise. In the bias voltages where channel mobility is nearly constant, the measured input-referred noise power is practically constant. Below threshold voltage, a reduction is observed in the input-referred noise as gate voltage is decreased, corresponding to the prediction of the model and due to the exponential reduction of the inversion capacitance with gate voltage. This behavior is observed for both n -mos and p -mos transistors. |
| Databáze: | OpenAIRE |
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