| Autor: |
Dmitry Morozov, Mikhail M. Pilipko, Ivan Piatak |
| Rok vydání: |
2015 |
| Předmět: |
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| Zdroj: |
2015 International Siberian Conference on Control and Communications (SIBCON). |
| DOI: |
10.1109/sibcon.2015.7147185 |
| Popis: |
A 14-bit 50-MS/s pipelined analog-to-digital converter (ADC) is presented. Operational amplifier (op-amp) sharing technique, 1.5 bit redundant stages based on switched capacitor circuits with inverter-based comparators and digital gain error calibration are used to reduce power consumption of the ADC and relax op-amp requirements. Simulation results in MATLAB/Simulink (structure level) and Cadence Virtuoso (schematic level, 180 nm 1.8 V CMOS) are provided. The pipelined ADC achieves 70 dB SINAD/80 dB SFDR and consumes 135 mW at 1.8 V supply, FoM is 1.04 pJ/conv. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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