Compact FPGA-Based Systolic Array Architecture for Motion Estimation Using Full Search Block Matching

Autor:	M. Arias-Estrada, G. Saldaha
Rok vydání:	2007
Předmět:	Router Computer science business.industry Motion estimation Bandwidth (signal processing) Chaining Systolic array Parallel computing business Field-programmable gate array Computer hardware Data compression Block (data storage)
Zdroj:	2007 3rd Southern Conference on Programmable Logic.
DOI:	10.1109/spl.2007.371756
Popis:	Motion estimation constitutes a significant computational part of video compression standards such as MPEG4. The present work focuses on the development of a reconfigurable systolic-based architecture implementing the full search block matching algorithm which is highly computing intensive and requires a large bandwidth to obtain real-time performance. The architecture comprises a smart memory scheme to reduce the number of access to image memory and router elements to handle data movement among different structures inside the same architecture, adding the possibility of chaining interconnection of multiple processing blocks. Every PE in the array includes a double ALU in order to search multiple macro-blocks in parallel. Results show that a peak performance in the order of 9 GOPS can be achieved.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::675e93b13f930cee721f65e6d2e9a706 https://doi.org/10.1109/spl.2007.371756 Zobrazit plný text záznamu