Fault-tolerant programmable logic array for nanoelectronics
| Autor: | Jacek Flak, Mika Laiho |
|---|---|
| Rok vydání: | 2012 |
| Předmět: |
Engineering
business.industry Applied Mathematics Logic family Macrocell array Programmable logic array Computer Science Applications Electronic Optical and Magnetic Materials Programmable logic device Programmable Array Logic Logic synthesis Computer engineering Electrical and Electronic Engineering Erasable programmable logic device business Simple programmable logic device Computer hardware |
| Zdroj: | International Journal of Circuit Theory and Applications. 40:1233-1247 |
| ISSN: | 0098-9886 |
| DOI: | 10.1002/cta.1795 |
| Popis: | This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single-electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies. Copyright © 2012 John Wiley & Sons, Ltd. |
| Databáze: | OpenAIRE |
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