| Autor: |
Chia-Juan Tsai, Sung-Ching Chi, Rui-Sheng Chen, Jian-Jia Tseng, Chun-Kai Tseng, Yu-Jung Liao, Ya Yuan Yang, Hsin-Chia Yang |
| Rok vydání: |
2019 |
| Předmět: |
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| Zdroj: |
2019 8th International Conference on Innovation, Communication and Engineering (ICICE). |
| DOI: |
10.1109/icice49024.2019.9117359 |
| Popis: |
Electrical performances, closely associated with dimensional structures and various processing conditions, are mainly manifested by I-V curves (Drain current (I DS ) versus Drain bias (V DS ) or Gate bias (V GS )). FinFET transistors use fin-structures as channels with channel widths equal to double the fin height plus the fin width. Without critical dimensional losses (CD losses) after the ionic dry etching or after development on photo resist, characteristics curves definitively behave according to the originally proposed. Unfortunately, CD losses may cause outrageous deviations from the previously proposed layout design, and thus crucially influence the electrical behaviors. Three fin widths are essentially planned, but there show analytically unreasonable I-V curves for FinFET transistors with fin widths W=0.110 micron and W=0.115micron on both NFinFET and PFinFET transistors. The conclusions help focus on FinFET transistors with fin width W=0.120 micron. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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