A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique
| Autor: | Jong-Kee Kwon, Young Kyun Cho, Young-Deuk Jeon, Jae-Won Nam |
|---|---|
| Rok vydání: | 2011 |
| Předmět: |
Differential nonlinearity
business.industry Computer science General Engineering Skew Successive approximation ADC Integrating ADC Effective number of bits Least significant bit CMOS Sampling (signal processing) Hardware_INTEGRATEDCIRCUITS Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES business Computer hardware |
| Zdroj: | Microelectronics Journal. 42:1225-1230 |
| ISSN: | 0026-2692 |
| Popis: | This paper presents a 12-bit 200-MS/s dual channel pipeline analog-to-digital converter (ADC). The ADC is featured with a digital timing correction for reducing a sampling skew and the capacitor swapping for suppressing nonlinearities at the first stage in the pipelined ADC. The prototype ADC occupies 0.8x1.4mm^2 in a 65-nm CMOS technology. The differential nonlinearity is less than 1.0 least significant bit with a 200MHz sampling frequency. With a sampling frequency of a 200-MS/s and an input of a 2.4MHz, the ADC, respectively, achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 61.49dB-70.71dB while consuming of 112mW at a supply voltage of 1.1V. |
| Databáze: | OpenAIRE |
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