An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder

Autor:	Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
Rok vydání:	2015
Předmět:	biology Computer science Turbo Data_CODINGANDINFORMATIONTHEORY Parallel computing Code rate biology.organism_classification Reduction (complexity) Soft-decision decoder Turbo equalizer Electrical and Electronic Engineering Throughput (business) Critical path method Decoding methods
Zdroj:	IEEE Transactions on Circuits and Systems II: Express Briefs. 62:65-69
ISSN:	1558-3791 1549-7747
DOI:	10.1109/tcsii.2014.2362733
Popis:	This brief presents an area-efficient turbo decoder based on the reciprocal dual trellis. In this brief, the radix-4 structure is introduced into the reciprocal dual trellis for throughput enhancement, and a sign-arrangement technique is developed to simplify the hardware and reduce the critical path of the recursion metric unit. To further reduce the hardware complexity, a time-multiplexing method with no degradation of throughput is also presented to save half of the extrinsic units, leading to a 15% hardware reduction of the soft-in/soft-out decoder. After implementation by CMOS 90-nm process, the proposed turbo decoder containing 600 $k$ -gates and 152-kb SRAM can achieve 425 Mb/s with 310-mW power consumption at 8/9 code rate. The post-simulation results show that the proposed methods provide a hardware-efficient solution for turbo decoders exploiting high-code-rate operations.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::66631c77913e0ffbd9871d43be6290bd https://doi.org/10.1109/tcsii.2014.2362733 Zobrazit plný text záznamu