Real time failure analysis of Cu interconnect defectivity through bitmap overlay analysis

Autor:	H. Nguyen, V.R. Sheth, A.M. Miscione, Phuong Nam Dao
Rok vydání:	2003
Předmět:	Engineering Interconnection business.industry Process (computing) Copper interconnect Overlay computer.file_format Root cause Reliability engineering Megabit Bitmap Static random-access memory business computer
Zdroj:	10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295).
DOI:	10.1109/asmc.1999.798169
Popis:	Bitmap to in-line defect overlay analysis was performed on a 4 Mbit SRAM memory array, which uses copper interconnect. This analysis provides an effective method of identifying killer copper defects, which inhibit product yield. It has been shown that bitmap overlay (BMOL) analysis is a very effective way of identifying killer defects for any technology at any process step. This can be proven to be a very powerful tool to relate physical defectivity to significant yield loss mechanisms. It has been shown that BMOL can be used to assign a root cause mechanism or a defect to an actual electrical fail without incurring tedious hours of destructive failure analysis. Failure analysis was, however, used to initially verify and confirm root cause of the electrical failures identified by BMOL analysis.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::6588e61d7268515af080dd2194d26b5f https://doi.org/10.1109/asmc.1999.798169 Zobrazit plný text záznamu