Predictive yield modeling for reconfigurable memory circuits

Autor:	M. Renfro, Rakesh Vallishayee, Xiaolei Li, R.K. Nurani, Andrzej J. Strojwas, Dennis Ciplickas, R. Williams
Rok vydání:	2002
Předmět:	Dynamic random-access memory business.industry Computer science Semiconductor memory computer.file_format Integrated circuit layout Memory controller Flash memory law.invention law Electronic engineering Redundancy (engineering) Bitmap Memory refresh business computer Computer hardware
Zdroj:	IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168).
DOI:	10.1109/asmc.1998.731368
Popis:	This paper presents a novel approach to the modeling of defect related yield losses in reconfigurable memory circuits. The proposed approach is based on the critical area extracted from the memory layout and the in-line defect inspection data. A complete chip level yield model that takes into account the actual redundancy scheme is presented, with the demonstration of excellent accuracy between the model prediction and bitmap data from an actual flash memory product manufactured by Intel Corporation.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::64a3f08116c7562624af05345d332e54 https://doi.org/10.1109/asmc.1998.731368 Zobrazit plný text záznamu