A 1.33 $\mu{\rm W}$
| Autor: | Zhuo Chao Sun, Kin Wai Roy Chew, Liter Siek, Howard Tang |
|---|---|
| Rok vydání: | 2014 |
| Předmět: |
Physics
business.industry Biomedical Engineering Electrical engineering Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY Chip Capacitance law.invention Capacitor Effective number of bits law Hardware_INTEGRATEDCIRCUITS Clock generator Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Image sensor business Voltage |
| Zdroj: | IEEE Transactions on Biomedical Circuits and Systems. 8:844-856 |
| ISSN: | 1940-9990 1932-4545 |
| DOI: | 10.1109/tbcas.2014.2300186 |
| Popis: | This paper presents a chip level 9 bits Charge Folding Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) to be used in a CMOS image sensor for retinal prosthesis. It has a maximum single-ended input range of 1.8 V but only uses a supply voltage of 0.9 V for the entire ADC through the Charge Folding method. Therefore, the input range is no longer limited by the supply rail as in conventional SAR ADC. Moreover, the ADC is controlled by an internal delay line based Asynchronous Clock Generator which can be programmed to adjust the resolution of the ADC from 5 to 9 bits. Therefore, resolution adaptation function can be applied to improve the energy efficiency up to 15%. The test chip is implemented in 0.18 $\mu{\rm m}$ CMOS process and occupies an area of 0.15 ${\rm mm}^{2}$ . At 0.9 V and 100 kS/s, the 9 bit s ADC consumes 1.33 $\mu{\rm W}$ and achieves an energy efficiency of 51.3 fJ/conversion-step . In addition, the power consumption can be further reduced by scaling the supply voltage and sampling frequency. At 100 kS/s, this ADC is capable of converting the input signal at a rate equivalent to 30 frames/s for a pixel array up to 3200 pixels. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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